Ring counter apparatus

ABSTRACT

A plurality of low-speed flip-flops connected to provide highspeed ring-counter-type operation through the use of parallel operating ring counter and shift register stages. The circuit also comprises means for assuring one and only one logic 1 in the device.

1 Elite States atem 1 1 3,639,74fi

Escoifier et al. 1 Feb. 1, 1972 54] R1113 COUNTER APPARATUS 3,280,343 101966 Kuhl ..307 223 x 3,329,834 7/1967 Klinikowski .307/223 X [72]lnvemm QQ' L ti fjzgg' gg Y g 1'; 3,513,329 5/1970 Washizuka et al.....307/223 v [73] Assignee: Collins Radio Company, Dallas, Tex. OTHERPUBLICATIONS [22] Filed: July 15, 1970 Maasberg, Self-Correcting,Synchronizable Ring Counter, IBM Technical Disclosure Bulletin, Vol. 10,No. 3, August 1 PP 54,959 1967,pp. 232-234.

1521 u.s.c1 ..23s/153,307/223,32s/43 Primary Examinercharles R Atkinson511 1m. 01 ..Gllc 29/00, G06f 1 1/00 AtwrneyRobefl Crawford and BruceLutz [58] FieldofSearch ..340/146.1;235/153;307/223;

328/43 ABSTRACT A plurality of low-speed flip-flops connected to providehigh- [56] References Cited speed ring-counter-type operation throughthe use of parallel UNITED STATES PATENTS operating ring counter andshift register stages. The circuit also comprises means for assuring oneand only one logic 1 in 3,184,612 5/1965 Petersen ..307/223 x thedevice. 3,163,847 12/1964 OConnor,.lr.. 3,217,185 1 H1965 Jansons..307/223 X 6 Claims, 1 Drawing Figure RING COUNTER APPARATUS Thepresent invention is concerned primarily with electronic circuits andmore specifically with a circuit which performs the functions of ahigh-speed ring counter while utilizing lower speed flip-flop devices.

The prior art has many types of ring counters but they have been subjectto two failings. One is the possibility of more than one logic Icirculating in the ring counter so that the devices being actuated fromthe ring counter are actuated more than once per cycle. A furtherpossibility is that the ring counter might be turned on with no logic lsin the loop. This of course would fail to actuate any device connectedto the ring counter. A further problem with prior art ring countercircuits is that as the clock speeds increase, the repetition period inthe clocking signal eventually becomes as small as the delay inherent inthe flip-flops being used in the ring counter. This, of course, createsproblems in the consecutive clocking of the flip-flops.

The above problems have been solved by the present invention wherein aspecial auxiliary circuit is utilized in conjunction with the flip-flopsto eliminate all but one logic 1 in the ring counter circuit and toassure that there will be one logic I in the circuit. In addition, thecircuit is designed such that one or more shift registers may beconnected to operate in parallel with the ring counter such that thepulsingor counting-type operation will still be obtained at high speedswhile the clocking of any individual set of flip-flops occurs at a lowerspeed.

It is therefore an object of the present invention to provide improvedring-counter-type circuitry.

Other objects and advantages of the present invention may be ascertainedfrom a reading of the specification and claims in conjunction with theappended drawing which shows a schematic block diagram includingwaveforms of a preferred embodiment of the invention.

A clock input signal is applied to lead in the drawing which isconnected to C-inputs of each of a plurality of flipflops labeled 12-26in the drawing. The clock input is also applied to a first terminal ofan AND-gate 28 which receives a second input from flip-flop ILA clockfalse signal which is designated in the drawing as CLK is connected to aline 30 which is further connected to the C-inputs of a plurality offlip-flops numbered 32-46. AND-gate 28 has an output connected throughan inverter 29 to an R-input of flip-flop 32. Each of the abovereferenced flip-flops has an unconnected output terminal at the upperright-hand portion thereof. In the flip-flops this terminal is labeledF. As is well known to those skilled in the art, a .lK flip-flop such asshown operates in the same fashion whether the set and reset pluses areapplied to the R- and S-inputs or vice versa. in other words, anegativegoing pulse supplied to either one of these terminals willprovide a positive-going output at the adjacent F- or T-terminals,respectively. Therefore, the upper terminal will be defined as true andthe lower as false regardless of letter designations placed there by themanufacturer of the flip-flops. The ring counter portion of this circuitcomprises flip-flops 12-26 wherein the output of each stage is connectedto the input of each of the following stages. As shown, the upper andlower output terminals of each stage are connected to the upper andlower input terminals of the following stage. The shift register portioncomprises a first stage 32 having the K-input connected to ground andthe J-input connected to a logic 1 voltage level which is shown as apositive potential. Each of the following stages has its input connectedto the output of the previous stage. The final stage 46 merely has anoutput connected to the upper terminal. A NAND-gate 48 has direct inputsfrom the T or lower output terminal of each of the first six stages12-22. It also receives an input from a reversing switch 50. Reversingswitch 50 has an input connected to a positive terminal 52 and an inputconnected to the T-output terminal of flip-flop 24. The operation ofswitch 50 is in conjunction with a further switch 54 operativelyconnecting S of flip-flop 24 between the S-inputs of flip-flops 14-22and an R-input of flip-flop 26. An output of NAND-gate 48 is connectedthrough an inverter 56 to a first input of a further NAND-gate 58 toprovide a false output thereto indicative of the signal from NAND-gate48. NAND-gate 58 is connected to receive a plurality of further inputsone of which is a clock (the same as or similar to that on lead 10) andthe other two of which are from the reversing switch 50 and the T-outputof the flip-flop 26. An output of NAND-gate 58 is connected to theR-input of flip-flop 26 and also to one of the contacts of switch 54.

With the switch 54 in the condition shown, the reversing switch 50operates to connect the T-terminal of flip-flop 24 to the lower input ofNANd-gate 48 and the positive terminal 52 to the second from the topinput of NAND-gate 58. When switch 54 is in the other position,reversing switch 50 connects positive terminal 52 to the input ofNAND-gate 48 and the T or lower output of flip-flop 24 to the input ofNAND-gate 58. For initial discussion purposes the circuitry comprisingNAND-gates 48 and 58 may be disregarded and it may be assumed that thering counter has only one logic I circulating therein. As each clockpulse is received on line 10, a clock is received at the C-input of eachof the flip-flops 12-26. However, the .IK flip-flops operate in responseto a clock pulse only in conjunction with an input on each of the J- andK-inputs. These inputs must be of the opposite polarity. Thus, only theflip-flop which is receiving an output from the previous stage willreact to the clock input. A given delay time after application of theclock input, the succeeding stage will be in condition for reacting tothe next clock pulse. Normal operation of flip-flops comprises utilizingonly either the leading or trailing edge of the clock pulse inconjunction with a given polarity signal at K and its inverse signal atJ.

The waveforms shown in conjunction with the drawing illustrate thatflip-flop 26 has an output as shown which provides a logic 1 input tothe K-terminal of flip-flop 12. On the next negative-going pulse of theclock, the logic l signal applied to the K-input and the logic 0 signalapplied to the J-input will cause flip-flop 12 to switch or be activatedso that its output at the F-terminal is as shown. Thus, a logic 1 inputwill be supplied to AND-gate 28. When the clock becomes positive therewill be two logic 1 inputs to AND-gate 28 and a logic 0 output willoccur to activate flip-flop 32 through the inverted output of inverter29. Since the OCR applied to terminal 30 is the inverse of the clocksignal applied to lead 10, the flip-flop 14 will be activated ahalf-clock-cycle later than flip-flop 32 and subsequently flip-flop 34will be activated another half-clockcycle later. When the flip-flop 46is activated, its output does not activate any further flip-flops butrather the shift register waits until flip-flop 12 is again activated bythe output of flipflop 26.

A practical application of the circuit shown may have its outputsconnected to the stages of a storage register such that each successivestage of the storage register is activated to receive a bit of datainformation. The first stage of the storage register would be connectedto flip-flop 12 while the second stage would be connected to flip-flop32. In this manner a sequential operation of the connected load isobtained at a higher rate than could be obtained by a ring counterhaving 16 stages instead of the eight as shown for each of the ringcounter and the shift register.

Even higher speed operation is possible by adjusting the clocking pulseto further shift registers such that each shift register group operatesat a prescribed intermediate time to the operation of similar stages inthe ring counter. Of course, the preferred embodiment is as shown butother embodiments may conceivably utilize different numbers of stages inthe shift registers than would be utilized in the ring counter.

The process of clearing the ring counter so that it has one and only onelogic I output as previously mentioned will now be described. For thepurpose of explaining the operation, a logic 0 output from the upperterminal will be described as a normal" output while a logic 1 from theupper terminal will be an odd" output. The embodiment to be firstdescribed will be that utilizing the switches 50 and 54 in the conditionshown. As is known, a NAND gate will provide a logic 0 output only ifall of the inputs are logic 1 Thus, since the inputs to NAND-gate 48 areconnected to the lower terminals of each of the first seven flip-flopsof the ring counter, a logic output will be obtained from NAND-gate 48only when each of the first seven flip-flops are in a normal condition.A logic 0 output from NAND-gate 48 results in a logic I being applied toNAND-gate 58 and to the S-input of flip-flop 26 because of inverter S6.A logic 1 input to the S-terminal of flip-flop 26 has no effect. IfNAND-gate 58 also receives a logic 1 input from terminal 52 throughswitch 50 and a logic 1 input from flipfiop 26 indicating that all thestages have a normal output, the next positive clock signal will providea logic 0 output from NAND-gate 58 thereby resetting the flip-flop 26 toan odd" condition. If on the other hand, the flip-flop 26 had an outputalready, there would be a logic 0 output at terminal T and thus theoutput of NAND-gate 58 would not go to logic 0. Thus, the two conditionsof all logic 0 outputs from the ring counter or a logic 1 only on thefinal stage have been taken care of.

A further possibility is more than one logic 1. The explanation utilizedfor clearing the extra logic ls is also applicable to an all logic lssituation. If there is one or more odd" outputs from the first sevenstages of the flip-flop, the NAND-gate 48 must of necessity have a logic1 output which will be inverted by inverter 56 to provide a logic 0 toNAND-gate 58 and to the S-input of flip-flop 26. This will causeflip-flop 26 to have a normal" output since it will be setting theT-terminal to a logic I. The next clock will set flip-flop 12 to anormal output since no input is received from flip-flop 26. Thus, everytime that there is a clock pulse and NAND-gate 48 receives signalsindicating that one or more of the first seven stages has an odd output,the final stage 26 is set to a normal condition. The logic Os thusprogress down the line of flip-flops until each of the first sevenstages are set to a normal condition and this leaves stage 26 with anodd output so that the ring counter is in the proper condition. In noinstance will it take more than eight clock pulses to assure that thering counter is in the proper condition. The shift register would alsobe clearing itself during this same eight clock-pulse time period sincethe first stage 12 is prevented from having a logic 0 output after thefirst clock pulse due to the setting to a normal condition of finalstage 26.

Design conditions for the present invention indicated that in someinstances (not pertinent to the disclosure) it may be desirable to resetthe last two stages. In such a situation the NAND-gate 48 would normallybe designed with only six inputs. However, to provide a universalillustration, the switch 50 is used to provide a logic 1 input toNAND-gate 48 from terminal 52 and provide the F-output of flip-flop 24to logic 1 input of NANDgate 58. As previously indicated the switch 54is moved to the opposite condition simultaneously with the operation ofreversing switch 50. in this situation, the occur rence of one or moreodd" outputs from the first six stages will set flip-flop 26 to anormal" condition. When each of the first six stages is in a normalcondition, a logic 1 will appear at the lower input of NAND-gate 58.lfonly one of stages 24 and 26 is in an odd condition, NAND-gate 58 willnot be activated. However, if both flip-flops 24 and 26 are in a normalcondition, NAND-gate 58 is activated upon the next clock pulse andflip-flop 26 is set to an odd" condition and flip-flop 24 is set to anormal" condition. The only other possibility is that both flip-flops 24will be in an odd condition. In such an instance no action will occur.However, the next clocl: pulse will place flip-flops l2 and 26 in an oddcondition thereby providing an output from NAND-gate 48 of a type toreset flip-flop 26 to a normal condition thus leaving the only flip-flopin an odd" condition as flip-flop 12.

A reset input is designated as 60 and is connected to set stage 12 in alogic 1 or odd" condition and stages 14-24 in a normal condition. Whilethis reset could also be applied to all the S-terminals of flip-flops32-46, taking into account the timing of the clock pulses applied tolead 30, such a connection was not necessary in the present applicationof this circuit. If such resetting of all of the flip-flops isnecessary, it

must be realized that a delay of approximately one-half of a full cycleof a clocking pulse (which would be identical to the time period betweenthe occurrence of an output signal on the F-terminals of flip-flops 12and 32) would be necessary between the application of the reset signalto lead 60 and the subsequent application of a reset signal for'theshift register flip-flops 32-46. This input enables the resetting of thecounter to a prescribed condition at any given time. Diode logic couldbe used to also set stage 26 to a normal" condition with this resetinput. For the application of the ring counter by the applicant, thefact that stage 26 might not be in a normal" condition upon reception ofa reset pulse did not render any inconvenience since immediately afterflip-flop 12 is placed in an odd" condition, an output is obtained fromNAND-gate 48 to set stage 26 in a normal condition. Thus, the entirering counter has only one odd output a very short period of time afterthe occurrence of a reset pulse on line 60.

While only two embodiments of the present invention have been shown anddescribed through the utilization of reversing switch 50 in conjunctionwith switch 54, it is to be realized that other embodiments such asmentioned in conjunction with the use of more than one parallel shiftregister is within the scope of the invention. Thus, we wish to belimited not by the description but only by the scope of the appendedclaims.

We claim:

1. Apparatus for providing a sequentially occurring and continuouslyoperating pulse train comprising, in combination:

ring counter means comprising N-stages;

shift register means comprising N-stages;

means for supplying clock signals to said ring counter means and to saidshift register means whereby said shift register means is clockedintermediate the clocking of two adjacent stages of said ring countermeans; and

gating means connected to receive inputs from said clock means and fromthe output of one of the stages of said ring counter means and connectedto a first stage of said shift register means for activating the firststage of said shift register means intermediate the operation of thefirst and second stages of said ring counter means.

2. Apparatus as claimed in claim 1 wherein:

said means for providing clock signals provides opposite phase signalsto said ring counter means and said shift register means; and

said first stage of said shift register means is activated halfwaybetween the operation of said first and second stages of said ringcounter means. 3. The method of assuring the occurrence of one and onlyone odd" output from a ring counter capable of having either a normal"or odd" output from each stage of N-stages thereof comprising the stepsof:

periodically sampling the outputs of a first portion of the stages andsetting the final stage of the ring counter to a normal" outputeachsampling period until all of said first portion of stage outputs providenormal" outputs; and

sampling the remaining portion of said N-stages of the ring counter whensaid first portion of stages are all in a normal" output condition toset one of the remaining portion of stages in an odd" condition and anyremaining stages in a normal condition if at the sample time each of theoutput stages are in a normal" condition.

4. Apparatus for assuring the occurrence of one and only one odd" outputfrom an N-stage ring counter means each stage of which may provideeither a normal" or odd output and wherein the N-stages are divided intoM- and R-stage portioris comprising, in combination:

first detection means connected to the M-portion stages of said ringcounter means for providing an output for periodically resetting a givenone of the R-portion stages of said ring counter means to a normaloutput condition if one or more of said M-portion stages are in an odd"condition; and

each of said stages have true and false outputs; and

said first detection means comprises NAND-gating means connected to thefalse outputs of said N-portion stages and said second detection meanscomprises NOR-gating means connected to receive the false outputs ofsaid R- portion stages of said ring counter means and a false output ofsaid first NAND-gating means.

1. Apparatus for providing a sequentially occurring and continuouslyoperating pulse train comprising, in combination: ring counter meanscomprising N-stages; shift register means comprising N-stages; means forsupplying clock signals to said ring counter means and to said shiftregister means whereby said shift register means is clocked intermediatethe clocking of two adjacent stages of said ring counter means; andgating means connected to receive inputs from said clock means and fromthe output of one of the stages of said ring counter means and connectedto a first stage of said shift register means for activating the firststage of said shift register means intermediate the operation of thefirst and second stages of said ring counter means.
 2. Apparatus asclaimed in claim 1 wherein: said means for providing clock signalsprovides opposite phase signals to said ring counter means and saidshift register means; and said first stage of said shift register meansis activated halfway between the operation of said first and secondstages of said ring counter means.
 3. The method of assuring theoccurrence of one and only one ''''odd'''' output from a ring countercapable of having either a ''''normal'''' or ''''odd'''' output fromeach stage of N-stages thereof comprising the steps of: periodicallysampling the outputs of a first portion of the stages and setting thefinal stage of the ring counter to a ''''normal'''' output each samplingperiod until all of said first portion of stage outputs provide''''normal'''' outputs; and sampling the remaining portion of saidN-stages of the ring counter when said first portion of stages are allin a ''''normal'''' output condition to set one of the remaining portionof stages in an ''''odd'''' condition and any remaining stages in a''''normal'''' condition if at the sample time each of the output stagesare in a ''''normal'''' condition.
 4. Apparatus for assuring theoccurrence of one and only one ''''odd'''' output from an N-stage ringcounter means each stage of which may provide either a ''''normal'''' or''''odd'''' output and wherein the N-stages are divided into M- andR-stage portions comprising, in combination: first detection meansconnected to the M-portion stages of said ring counter means forproviding an output for periodically resetting a given one of theR-portion stages of said ring counter means to a ''''normal'''' outputcondition if one or more of said M-portion stages are in an ''''odd''''condition; and second detection means connected to said R-portion stagesand to said first detection means for resetting one of said R-portionstages to an odd condition and any remaining R-portion stages to anormal condition when all of said N-stages are in a normal condition. 5.Apparatus as claimed in claim 4 wherein said R-portion comprises oneflip-flop stage.
 6. Apparatus as claimed in claim 4 wherein: each ofsaid stages have true and false outputs; and said first detection meanscomprises NAND-gating means connected to the false outputs of saidN-portion stages and said second detection means comprises NOR-gatingmeans connected to receive the false outputs of said R-portion stages ofsaid ring counter means and a false output of said first NAND-gatingmeans.